Questions

Suppose your flip-flop is positive edgetriggered. time for which data should be stable prior to positive edge clock is called setup is called setup time constraint.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

If any of these constraints are violate d then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb > Tskew + Thold

2. Tcq + Tcomb > Tskew + T - Tsetup

Tcq is time delay when data enters the flip flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop, if clock reaches first to source flip flop and then after some delay to destination flip flop, it is positive skew and if vice versa then negative  skew. 

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

Yaounde is the capital of Cameroon

Because of high stability, large Q (Quality Factor) & the frequency that doesn't drift with aging. Crystal is used as a clock source most of the times.

The Delhi government has recently approved 'Good Samaritan Policy' under which monetary incentive of Rs 2,000 and appreciation certificate will be given to people who help road accident victims in the national capital. The scheme is intended to encourage people to take accident victims in emergency situation to hospitals so that someone’s life could be saved.

A hard real-time system guarantees that critical tasks complete on time. This goal requires that all delays in the system be bounded from the retrieval of the stored data to the time that it takes the operating system to finish any request made of it. A soft real time system where a critical real-time task gets priority over other tasks and retains that priority until it completes. As in hard real time systems kernel delays need to be bounded