Questions

Suppose your flip-flop is positive edgetriggered. time for which data should be stable prior to positive edge clock is called setup is called setup time constraint.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

If any of these constraints are violate d then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb > Tskew + Thold

2. Tcq + Tcomb > Tskew + T - Tsetup

Tcq is time delay when data enters the flip flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop, if clock reaches first to source flip flop and then after some delay to destination flip flop, it is positive skew and if vice versa then negative  skew. 

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

There are situations, called hazards, that prevent the next insturction in the instruction stream from executing during its designated clock cycle. hazards reduce the performance from the ideal speedup gained by pipelining.

There are three classes of Hazards:

1. Structural hazards: It arise from resource conficts when the hardware cannot support all possible combinations of instructions simultaniously in overlapped execution.

2. Data Hazards: It arise when an instruction depends on the results of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.

3.control hazards. it arise from the pipelining of branches and other instructions that chage the PC.

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