Questions

Madhya Pradesh has become the first Indian state to announce shifting of its financial year format to January-December starting from 2018, as against the current practice of April-March cycle. The decision has recently taken by the state government in its state cabinet meeting, which was chaired by Chief Minister Shivraj Singh Chouhan. Thus, the budget session of the next financial year would be held in December-January 2018.

Suppose your flip-flop is positive edgetriggered. time for which data should be stable prior to positive edge clock is called setup is called setup time constraint.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

If any of these constraints are violate d then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb > Tskew + Thold

2. Tcq + Tcomb > Tskew + T - Tsetup

Tcq is time delay when data enters the flip flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop, if clock reaches first to source flip flop and then after some delay to destination flip flop, it is positive skew and if vice versa then negative  skew. 

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

From the given conditions ,

only A = 27 yrs satisfies.